1. Field of the Invention
The present invention relates to a fin type electrostatic discharge (ESD) protection device, and more particularly, to a fin type ESD protection device having high channel resistance for better ESD protection ability.
2. Description of the Prior Art
The conventional planar metal-oxide-semiconductor (hereinafter abbreviated as MOS) transistor has difficulty when scaling down to 65 nm and below. Therefore, the non-planar transistor technology such as Fin Field effect transistor (hereinafter abbreviated as FinFET) technology that allows smaller size and higher performance is developed to replace the planar MOS transistor. For example, dual-gate FinFET device, tri-gate FinFET device, and omega-FinFET device have been provided. Furthermore, gate-all-around (GAA) nanowire FET device is progressed for achieving the ongoing goals of High performance, low cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits. However, the FinFET suffers electrostatic discharge (ESD) issues because the ESD current tends to flow through the relatively smaller fin channel region and cause damage to the FinFET, and the fin type device has to be further modified for enhancing the ESD protection ability.